rewire-backend-2.8: A Haskell-to-Verilog/VHDL compiler, the Hyle backend

Index

Add 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
AlwaysReWire.Verilog.Syntax
AlwaysCombReWire.Verilog.Syntax
And 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
AShrReWire.Hyle.Syntax
Assign 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
bFalseReWire.Verilog.Syntax
Bind 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Cryptol.Syntax
BinOpReWire.Cryptol.Syntax
BitReWire.Verilog.Syntax
Blind 
1 (Type/Class)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
BlockReWire.Verilog.Syntax
bTrueReWire.Verilog.Syntax
Call 
1 (Data Constructor)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
CaseReWire.Verilog.Syntax
Cat 
1 (Data Constructor)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
cat 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
3 (Function)ReWire.Hyle.Syntax
CEqReWire.Verilog.Syntax
checkReWire.Hyle.Check
ChunkReWire.VHDL.Syntax
ChunkHexReWire.VHDL.Syntax
ChunkLitReWire.VHDL.Syntax
clockResetReWire.Hyle.ToVerilog
CNEqReWire.Verilog.Syntax
CombReWire.Hyle.Syntax
Comment 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
CompReWire.Cryptol.Syntax
compileProgram 
1 (Function)ReWire.Hyle.ToCryptol
2 (Function)ReWire.Hyle.ToVerilog
3 (Function)ReWire.Hyle.ToVHDL
Component 
1 (Type/Class)ReWire.VHDL.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
ConcatReWire.Verilog.Syntax
Cond 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Type/Class)ReWire.VHDL.Syntax
CondEqReWire.VHDL.Syntax
CondRisingReWire.VHDL.Syntax
ConstantReWire.VHDL.Syntax
cryptolNameReWire.Cryptol.Syntax
DeclReWire.Verilog.Syntax
dedupeReWire.Hyle.Transform
Defn 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Cryptol.Syntax
3 (Type/Class)ReWire.Hyle.Syntax
4 (Data Constructor)ReWire.Hyle.Syntax
defnAnnoteReWire.Hyle.Syntax
defnArgsReWire.Cryptol.Syntax
defnBody 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Hyle.Syntax
defnCommentsReWire.Cryptol.Syntax
defnDocReWire.Hyle.Syntax
defnName 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Hyle.Syntax
defnNoInlineReWire.Hyle.Syntax
defnParamsReWire.Hyle.Syntax
defnPortNamesReWire.Hyle.ToVerilog
defnQuantNReWire.Cryptol.Syntax
defnResTyReWire.Cryptol.Syntax
defnSigReWire.Hyle.Syntax
defnWhereReWire.Cryptol.Syntax
DelayReWire.Verilog.Syntax
devAnnoteReWire.Hyle.Syntax
devBodyReWire.Hyle.Syntax
Device 
1 (Type/Class)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Verilog.Syntax
3 (Type/Class)ReWire.Hyle.Syntax
4 (Data Constructor)ReWire.Hyle.Syntax
5 (Type/Class)ReWire.VHDL.Syntax
6 (Data Constructor)ReWire.VHDL.Syntax
devInputsReWire.Hyle.Syntax
devInstancesReWire.Hyle.Syntax
devNameReWire.Hyle.Syntax
devOutputsReWire.Hyle.Syntax
devRegistersReWire.Hyle.Syntax
devTagsReWire.Hyle.Syntax
devUnitsReWire.VHDL.Syntax
DirectionReWire.VHDL.Syntax
DisplayReWire.Verilog.Syntax
DivReWire.Verilog.Syntax
ElemReWire.VHDL.Syntax
ElementReWire.Verilog.Syntax
envDefnsReWire.Hyle.Interp
envExternsReWire.Hyle.Interp
Eq 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
evalExpReWire.Hyle.Interp
evalOpReWire.Hyle.Interp
Exp 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Type/Class)ReWire.Verilog.Syntax
3 (Type/Class)ReWire.Hyle.Syntax
4 (Type/Class)ReWire.VHDL.Syntax
extAnnoteReWire.Hyle.Syntax
Extern 
1 (Type/Class)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
ExternKindReWire.Hyle.Syntax
externResultSizeReWire.Hyle.Syntax
extGenericsReWire.Hyle.Syntax
extInputsReWire.Hyle.Syntax
extKindReWire.Hyle.Syntax
extModelReWire.Hyle.Syntax
extNameReWire.Hyle.Syntax
extOutputsReWire.Hyle.Syntax
FinishReWire.Verilog.Syntax
FunCallReWire.VHDL.Syntax
gatherReWire.Hyle.Syntax
GIdReWire.Hyle.Syntax
GtReWire.Verilog.Syntax
GtEqReWire.Verilog.Syntax
helpersReWire.Cryptol.Syntax
helpersPackageReWire.VHDL.Helpers
hoistInstancesReWire.Hyle.Transform
IEnv 
1 (Type/Class)ReWire.Hyle.Interp
2 (Data Constructor)ReWire.Hyle.Interp
If 
1 (Data Constructor)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Verilog.Syntax
3 (Data Constructor)ReWire.Hyle.Syntax
IfElseReWire.Verilog.Syntax
InReWire.VHDL.Syntax
Index 
1 (Data Constructor)ReWire.Cryptol.Syntax
2 (Type/Class)ReWire.Verilog.Syntax
3 (Type/Class)ReWire.Hyle.Syntax
4 (Type/Class)ReWire.VHDL.Syntax
InitialReWire.Verilog.Syntax
inlineReWire.Hyle.Transform
inlineByReWire.Hyle.Transform
InOutReWire.Verilog.Syntax
InputReWire.Verilog.Syntax
inputValueReWire.Hyle.Interp
InsReWire.Hyle.Interp
Instance 
1 (Type/Class)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
Instantiate 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
interpReWire.Hyle.Interp
isNil 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
3 (Function)ReWire.Hyle.Syntax
LAndReWire.Verilog.Syntax
lastComponentReWire.Hyle.ToVerilog
LenReWire.Cryptol.Syntax
LenSuccReWire.Cryptol.Syntax
LenVarReWire.Cryptol.Syntax
LetReWire.Hyle.Syntax
LineVarReWire.VHDL.Syntax
Lit 
1 (Data Constructor)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
3 (Data Constructor)ReWire.VHDL.Syntax
LitBitsReWire.Verilog.Syntax
LNotReWire.Verilog.Syntax
LocalParamReWire.Verilog.Syntax
LogicReWire.Verilog.Syntax
LOrReWire.Verilog.Syntax
LShiftReWire.Verilog.Syntax
LShiftArithReWire.Verilog.Syntax
LShrReWire.Hyle.Syntax
LtReWire.Verilog.Syntax
LtEqReWire.Verilog.Syntax
LVal 
1 (Type/Class)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Verilog.Syntax
3 (Type/Class)ReWire.VHDL.Syntax
LValsReWire.Verilog.Syntax
LVElemReWire.VHDL.Syntax
LVNameReWire.VHDL.Syntax
LVRangeReWire.VHDL.Syntax
mangleReWire.Hyle.Mangle
mangleFreshReWire.Hyle.Mangle
mangleModReWire.Hyle.Mangle
ModReWire.Verilog.Syntax
modComments 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
modDefnsReWire.Cryptol.Syntax
modName 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
modParamsReWire.Cryptol.Syntax
modPortsReWire.Verilog.Syntax
modSignalsReWire.Verilog.Syntax
modStmtReWire.Verilog.Syntax
Module 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Cryptol.Syntax
3 (Type/Class)ReWire.Verilog.Syntax
4 (Data Constructor)ReWire.Verilog.Syntax
mparens 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
Mul 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
Name 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Type/Class)ReWire.Cryptol.Syntax
3 (Type/Class)ReWire.Verilog.Syntax
4 (Type/Class)ReWire.Hyle.Syntax
5 (Type/Class)ReWire.VHDL.Syntax
NeReWire.Hyle.Syntax
NegReWire.Verilog.Syntax
NEqReWire.Verilog.Syntax
nil 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
3 (Function)ReWire.Hyle.Syntax
Not 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
NumReWire.VHDL.Syntax
OneReWire.Verilog.Syntax
OpReWire.Hyle.Syntax
opNameReWire.Hyle.Syntax
opResultSizeReWire.Hyle.Syntax
optimizeReWire.Hyle.Transform
Or 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
OutReWire.VHDL.Syntax
OutputReWire.Verilog.Syntax
OutsReWire.Hyle.Interp
Param 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Cryptol.Syntax
ParAssignReWire.Verilog.Syntax
Parenless 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Type/Class)ReWire.Verilog.Syntax
parenless 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.Verilog.Syntax
parseHyleReWire.Hyle.Parse
parseHyleDefnsReWire.Hyle.Parse
parseHyleTextReWire.Hyle.Parse
partialEvalReWire.Hyle.Transform
pgmModulesReWire.Verilog.Syntax
pickFreshReWire.Hyle.Mangle
Port 
1 (Type/Class)ReWire.Verilog.Syntax
2 (Type/Class)ReWire.VHDL.Syntax
3 (Data Constructor)ReWire.VHDL.Syntax
PosReWire.Verilog.Syntax
Pow 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
ppArmReWire.VHDL.Syntax
ppBinOpReWire.Verilog.Syntax
ppBitsReWire.VHDL.Syntax
ppCommaListReWire.Verilog.Syntax
ppComment 
1 (Function)ReWire.Verilog.Syntax
2 (Function)ReWire.VHDL.Syntax
ppContextReWire.VHDL.Syntax
ppDimsReWire.Verilog.Syntax
ppFunReWire.Cryptol.Syntax
ppHexReWire.VHDL.Syntax
ppInitReWire.VHDL.Syntax
ppItemReWire.Verilog.Syntax
ppLit 
1 (Function)ReWire.Cryptol.Syntax
2 (Function)ReWire.VHDL.Syntax
ppNameReWire.VHDL.Syntax
ppParamsReWire.Cryptol.Syntax
ppUnitReWire.VHDL.Syntax
ppUnOpReWire.Verilog.Syntax
ppVecTyReWire.VHDL.Syntax
PrimReWire.Hyle.Syntax
ProcessReWire.VHDL.Syntax
ProcVarReWire.VHDL.Syntax
progDefnsReWire.Hyle.Syntax
progDeviceReWire.Hyle.Syntax
progExternsReWire.Hyle.Syntax
Program 
1 (Type/Class)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
purgeDevLetsReWire.Hyle.Transform
purgeUnusedReWire.Hyle.Transform
purgeZeroWidthReWire.Hyle.Transform
RAndReWire.Verilog.Syntax
RangeReWire.Verilog.Syntax
RedAndReWire.Hyle.Syntax
RedOrReWire.Hyle.Syntax
RedXOrReWire.Hyle.Syntax
RegReWire.Verilog.Syntax
Register 
1 (Type/Class)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
RepReWire.Hyle.Syntax
ReplReWire.Verilog.Syntax
reservedWords 
1 (Function)ReWire.Hyle.Syntax
2 (Function)ReWire.VHDL.Syntax
resizeReWire.Cryptol.Syntax
RNAndReWire.Verilog.Syntax
RNorReWire.Verilog.Syntax
ROrReWire.Verilog.Syntax
RShiftReWire.Verilog.Syntax
RShiftArithReWire.Verilog.Syntax
runReWire.Hyle.Interp
RXNorReWire.Verilog.Syntax
RXOrReWire.Verilog.Syntax
sanitizeComment 
1 (Function)ReWire.Verilog.Syntax
2 (Function)ReWire.VHDL.Syntax
SAssignReWire.VHDL.Syntax
seedNamesReWire.Hyle.Mangle
SelAssignReWire.VHDL.Syntax
SensitivityReWire.Verilog.Syntax
SeqReWire.Hyle.Syntax
SeqAssignReWire.Verilog.Syntax
SeqLitReWire.Cryptol.Syntax
SeqStmtReWire.VHDL.Syntax
SExtReWire.Hyle.Syntax
SFinishReWire.VHDL.Syntax
SGeReWire.Hyle.Syntax
SGtReWire.Hyle.Syntax
ShlReWire.Hyle.Syntax
SIfReWire.VHDL.Syntax
Sig 
1 (Type/Class)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
SigCommentReWire.VHDL.Syntax
Signal 
1 (Type/Class)ReWire.Verilog.Syntax
2 (Type/Class)ReWire.VHDL.Syntax
3 (Data Constructor)ReWire.VHDL.Syntax
sigNameReWire.Verilog.Syntax
SignedReWire.Verilog.Syntax
SingReWire.Cryptol.Syntax
SInstInReWire.Hyle.Syntax
Size 
1 (Type/Class)ReWire.Cryptol.Syntax
2 (Type/Class)ReWire.Verilog.Syntax
3 (Type/Class)ReWire.Hyle.Syntax
4 (Type/Class)ReWire.VHDL.Syntax
SizeAnnotatedReWire.Hyle.Syntax
sizeOfReWire.Hyle.Syntax
SLeReWire.Hyle.Syntax
SLetReWire.Hyle.Syntax
Slice 
1 (Data Constructor)ReWire.Hyle.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
sliceReWire.Cryptol.Syntax
SLtReWire.Hyle.Syntax
SNextReWire.Hyle.Syntax
SOutputReWire.Hyle.Syntax
Stmt 
1 (Type/Class)ReWire.Verilog.Syntax
2 (Type/Class)ReWire.Hyle.Syntax
3 (Type/Class)ReWire.VHDL.Syntax
stripFreshTagReWire.Hyle.Mangle
Sub 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
subRangeReWire.Hyle.Interp
svReservedReWire.Hyle.Mangle
SWaitReWire.VHDL.Syntax
SWriteLnReWire.VHDL.Syntax
tagRegReWire.Hyle.ToVerilog
TBitsReWire.Cryptol.Syntax
TCallReWire.Cryptol.Syntax
testbench 
1 (Function)ReWire.Hyle.ToVerilog
2 (Function)ReWire.Hyle.ToVHDL
TruncReWire.Hyle.Syntax
TSeqReWire.Cryptol.Syntax
TyReWire.Cryptol.Syntax
UDivReWire.Hyle.Syntax
UGeReWire.Hyle.Syntax
UGtReWire.Hyle.Syntax
ULeReWire.Hyle.Syntax
ULtReWire.Hyle.Syntax
UModReWire.Hyle.Syntax
unBlindReWire.Hyle.Syntax
UndefReWire.Hyle.Syntax
Unit 
1 (Type/Class)ReWire.VHDL.Syntax
2 (Data Constructor)ReWire.VHDL.Syntax
unitCommentsReWire.VHDL.Syntax
unitComponentsReWire.VHDL.Syntax
unitNameReWire.VHDL.Syntax
unitPackagesReWire.VHDL.Syntax
unitPortsReWire.VHDL.Syntax
unitSignalsReWire.VHDL.Syntax
unitStmtsReWire.VHDL.Syntax
UnOpReWire.Cryptol.Syntax
UnsignedReWire.Verilog.Syntax
Value 
1 (Type/Class)ReWire.Verilog.Syntax
2 (Type/Class)ReWire.Hyle.Syntax
Var 
1 (Data Constructor)ReWire.Cryptol.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
3 (Data Constructor)ReWire.VHDL.Syntax
vhdlNameReWire.VHDL.Syntax
WCastReWire.Verilog.Syntax
WireReWire.Verilog.Syntax
WireAssignReWire.Verilog.Syntax
XReWire.Verilog.Syntax
XCallReWire.Hyle.Syntax
XNorReWire.Verilog.Syntax
XOr 
1 (Data Constructor)ReWire.Verilog.Syntax
2 (Data Constructor)ReWire.Hyle.Syntax
yamlPrefixesReWire.Hyle.Interp
ZReWire.Verilog.Syntax
ZeroReWire.Verilog.Syntax
ZExtReWire.Hyle.Syntax