rewire-backend-2.8: A Haskell-to-Verilog/VHDL compiler, the Hyle backend
Safe HaskellSafe
LanguageHaskell2010

ReWire.Hyle.Check

Description

Well-formedness checking for Hyle programs (doc/hyle.md, section 4): syntax-directed expression typing (every node's cached width is verified), declaration well-formedness, device scoping and exactly-once assignment coverage, and acyclicity of the call graph (including extern-model edges).

Documentation