| Safe Haskell | Safe |
|---|---|
| Language | Haskell2010 |
ReWire.VHDL.Syntax
Description
Syntax for the subset of VHDL-2008 emitted by the VHDL backend (ReWire.Hyle.ToVHDL). Everything is typed std_logic_vector; Verilog-style expression semantics (unsigned arithmetic, width rules) are provided by functions in an emitted rw_helpers package.
Synopsis
- type Name = Text
- type Size = Word
- type Index = Int
- newtype Device = Device {}
- data Unit = Unit {
- unitName :: !Name
- unitComments :: ![Text]
- unitPackages :: ![Text]
- unitPorts :: ![Port]
- unitComponents :: ![Component]
- unitSignals :: ![Signal]
- unitStmts :: ![Stmt]
- data Direction
- data Port = Port !Name !Direction !Size
- data Component = Component !Name ![Name] ![Port]
- data Signal
- ppComment :: Text -> Doc an
- sanitizeComment :: Text -> Text
- data Stmt
- data ProcVar = LineVar !Name
- ppArm :: (BV, Exp) -> Doc an
- data SeqStmt
- data Chunk
- data Cond
- = CondEq !Name !BV
- | CondRising !Name
- data LVal
- data Exp
- ppLit :: BV -> Doc an
- ppInit :: BV -> Doc an
- ppBits :: BV -> Text
- ppHex :: BV -> Text
- ppVecTy :: Size -> Doc an
- ppName :: Name -> Doc an
- vhdlName :: Name -> Text
- reservedWords :: HashSet Text
- ppUnit :: Unit -> Doc an
- ppContext :: [Text] -> Doc an
Documentation
An entity/architecture pair with its context clause (use clauses, e.g., ieee.std_logic_1164.all; library clauses are derived).
Constructors
| Unit | |
Fields
| |
Component declaration: name, integer generic names, ports.
Declarations in the architecture declarative part: signals with an optional initial value, constants, and display-only comment lines.
sanitizeComment :: Text -> Text Source #
Newlines in comment text would push the remainder into code position.
Constructors
| Assign !LVal !Exp | |
| SelAssign !Exp !LVal ![(BV, Exp)] !Exp | Selected signal assignment: scrutinee, target, choices, others. |
| Process ![Name] ![ProcVar] ![SeqStmt] | Sensitivity list (empty: none), variables, body. |
| Instantiate !Name !Name ![(Name, Integer)] ![(Name, Exp)] | Component, instance label, generic map, port map (empty name: positional). |
| Comment !Text |
Process-local variable declarations.
ppArm :: (BV, Exp) -> Doc an Source #
A selected-assignment choice: the choices are literal bit-strings of exactly the scrutinee's width (never constants or aggregates, for portability).
Sequential statements (process bodies).
Constructors
| SIf ![(Cond, [SeqStmt])] ![SeqStmt] | if/elsif branches, else branch. |
| SAssign !LVal !Exp | |
| SWait !Natural | wait for n ns; |
| SWriteLn ![Chunk] | write(l, ...); writeline(output, l); |
| SFinish | std.env.finish; |
A piece of a line written by SWriteLn: a string literal or the hex-string rendering of an expression.
Conditions appearing in generated processes.
Constructors
| CondEq !Name !BV | name = "bits" |
| CondRising !Name | rising_edge(name(0)) |
Constructors
| LVName !Name | |
| LVRange !Name !Index !Index | name(j downto i): low index i, high index j. |
| LVElem !Name !Index |
Constructors
| Lit !BV | |
| Var !Name | |
| Slice !Name !Index !Index | name(j downto i): low index i, high index j. |
| Elem !Name !Index | name(i downto i): a 1-bit vector. |
| Cat ![Exp] | |
| FunCall !Name ![Exp] | |
| Num !Natural |
ppLit :: BV -> Doc an Source #
A qualified bit-string literal: hex (std_logic_vector'(X"5a")) when the width is a whole number of hex digits, binary (std_logic_vector'(B"0101")) otherwise.
ppInit :: BV -> Doc an Source #
A literal in signal-initial position: like ppLit, except wide all-zero
vectors render as an aggregate.
ppName :: Name -> Doc an Source #
Print a name as a VHDL identifier: a basic identifier when valid (and unambiguous: all-lowercase, since basic identifiers are case-insensitive), otherwise a VHDL-2008 extended identifier (\name\).
reservedWords :: HashSet Text Source #