Documentation

Mangle a Hyle name into an identifier acceptable to the RTL backends (when it isn't one already): alphanumerics plus underscores and dollar signs (the VHDL pretty-printer further escapes names as needed).

Module names need to be de-conflicted because they aren't immediately freshened.

Pick an unused RTL identifier from an already-mangled seed, updating the used map: the seed itself when free, otherwise the first free suffix-numbered variant. Every picked (or seedNames-seeded) name is a key of the map, so a suffixed pick can never collide with a name issued later under its own seed; the value is the seed's next suffix number, keeping repeated requests O(1).

Seed a pickFresh used map with ambient names (ports, registers) that are emitted verbatim, without passing through the backend's fresh-name supply: generated names must not collide with them.

Strip the freshening suffixes stacked onto a name by the Hyle inliner ($i<digits>) and the fold-time instance hoist ($h<digits>), recovering the original base for display. Suffix groups stack (deep inline chains re-freshen already-freshened names, and hoisting re-lets inliner names), so stripping repeats; a name that is nothing but suffix (e.g. a bare legacy $i0) is kept unstripped rather than emptied.

SystemVerilog reserved words (IEEE 1800-2012, Annex B): generated Verilog identifiers must dodge them. (The VHDL backend needs no analogue: its pretty-printer escapes reserved words as extended identifiers.)