| Safe Haskell | Safe |
|---|---|
| Language | Haskell2010 |
ReWire.Verilog.Syntax
Synopsis
- newtype Device = Device {
- pgmModules :: [Module]
- type Name = Text
- type Size = Word
- type Index = Int
- type Value = Integer
- data Module = Module {
- modName :: Name
- modComments :: ![Text]
- modPorts :: [Port]
- modSignals :: [Signal]
- modStmt :: [Stmt]
- ppComment :: Text -> Doc an
- sanitizeComment :: Text -> Text
- data Port
- ppDims :: [Size] -> Doc an
- data Signal
- sigName :: Signal -> Name
- data Stmt
- = Always [Sensitivity] Stmt
- | AlwaysComb Stmt
- | Initial Stmt
- | IfElse Exp Stmt Stmt
- | If Exp Stmt
- | Case Exp [(Exp, Stmt)] Stmt
- | Assign LVal Exp
- | SeqAssign LVal Exp
- | ParAssign LVal Exp
- | WireAssign Size Name Exp
- | Decl Signal
- | LocalParam Size Name BV
- | Comment Text
- | Block [Stmt]
- | Instantiate Name Name [(Name, Exp)] [(Name, Exp)]
- | Delay Natural
- | Display Text [Exp]
- | Finish
- ppItem :: (Exp, Stmt) -> Doc an
- data Sensitivity
- data Exp
- = Add Exp Exp
- | Sub Exp Exp
- | Mul Exp Exp
- | Div Exp Exp
- | Mod Exp Exp
- | Pow Exp Exp
- | LAnd Exp Exp
- | LOr Exp Exp
- | And Exp Exp
- | Or Exp Exp
- | XOr Exp Exp
- | XNor Exp Exp
- | LShift Exp Exp
- | RShift Exp Exp
- | LShiftArith Exp Exp
- | RShiftArith Exp Exp
- | Not Exp
- | LNot Exp
- | RAnd Exp
- | RNAnd Exp
- | ROr Exp
- | RNor Exp
- | RXOr Exp
- | RXNor Exp
- | Eq Exp Exp
- | NEq Exp Exp
- | CEq Exp Exp
- | CNEq Exp Exp
- | Lt Exp Exp
- | Gt Exp Exp
- | LtEq Exp Exp
- | GtEq Exp Exp
- | Cond Exp Exp Exp
- | Concat [Exp]
- | Repl Exp Exp
- | WCast Size Exp
- | Signed Exp
- | Unsigned Exp
- | LitBits BV
- | LVal LVal
- class Parenless a where
- mparens :: (Pretty a, Parenless a) => a -> Doc an
- ppBinOp :: Exp -> Text -> Exp -> Doc an
- ppUnOp :: Text -> Exp -> Doc an
- bTrue :: Exp
- bFalse :: Exp
- data Bit
- data LVal
- ppCommaList :: [Doc an] -> Doc an
- cat :: [Exp] -> Exp
- nil :: Exp
- isNil :: Exp -> Bool
Documentation
Constructors
| Device | |
Fields
| |
Constructors
| Module | |
Fields
| |
sanitizeComment :: Text -> Text Source #
Newlines in comment text would push the remainder into code position.
Constructors
| Always [Sensitivity] Stmt | |
| AlwaysComb Stmt | |
| Initial Stmt | |
| IfElse Exp Stmt Stmt | |
| If Exp Stmt | |
| Case Exp [(Exp, Stmt)] Stmt | Scrutinee, case items, default item. |
| Assign LVal Exp | |
| SeqAssign LVal Exp | |
| ParAssign LVal Exp | |
| WireAssign Size Name Exp | Net declaration assignment: wire [n-1:0] x = e; |
| Decl Signal | A signal declaration in statement position. |
| LocalParam Size Name BV | |
| Comment Text | |
| Block [Stmt] | |
| Instantiate Name Name [(Name, Exp)] [(Name, Exp)] | |
| Delay Natural | #n; |
| Display Text [Exp] | $display("fmt", args); |
| Finish | $finish; |
data Sensitivity Source #
Instances
| Show Sensitivity Source # | |
Defined in ReWire.Verilog.Syntax Methods showsPrec :: Int -> Sensitivity -> ShowS # show :: Sensitivity -> String # showList :: [Sensitivity] -> ShowS # | |
| Eq Sensitivity Source # | |
Defined in ReWire.Verilog.Syntax | |
| Pretty Sensitivity Source # | |
Defined in ReWire.Verilog.Syntax | |
Constructors
| Add Exp Exp | |
| Sub Exp Exp | |
| Mul Exp Exp | |
| Div Exp Exp | |
| Mod Exp Exp | |
| Pow Exp Exp | |
| LAnd Exp Exp | |
| LOr Exp Exp | |
| And Exp Exp | |
| Or Exp Exp | |
| XOr Exp Exp | |
| XNor Exp Exp | |
| LShift Exp Exp | |
| RShift Exp Exp | |
| LShiftArith Exp Exp | |
| RShiftArith Exp Exp | |
| Not Exp | |
| LNot Exp | |
| RAnd Exp | |
| RNAnd Exp | |
| ROr Exp | |
| RNor Exp | |
| RXOr Exp | |
| RXNor Exp | |
| Eq Exp Exp | |
| NEq Exp Exp | |
| CEq Exp Exp | |
| CNEq Exp Exp | |
| Lt Exp Exp | |
| Gt Exp Exp | |
| LtEq Exp Exp | |
| GtEq Exp Exp | |
| Cond Exp Exp Exp | |
| Concat [Exp] | |
| Repl Exp Exp | |
| WCast Size Exp | |
| Signed Exp | $signed(e) |
| Unsigned Exp | $unsigned(e) |
| LitBits BV | |
| LVal LVal |
ppCommaList :: [Doc an] -> Doc an Source #
A comma-separated list; long lists (> 4 elements) may wrap at the page width (each separator is a softline, giving line-filling behavior).