The VHDL backend on Hyle, mirroring ReWire.Hyle.ToVerilog (the cosimulation check keeps the two aligned). With widths explicit and exact in the IR, the width-reconstruction machinery of the old backend (wcast/expWidth) disappears: every emitted expression already has exactly the width its context requires, and the rw_helpers package is needed only for the operations themselves (VHDL std_logic_vector has no arithmetic), not for resizing discipline.

Defn modules never take clock or reset ports (sequential externs are device-level instances). Extern ports connect by name; ports left anonymous in the source-level extern descriptor reach this backend with the p<i> names synthesized by the producer, which the hand-written VHDL implementations in the test suite already use.