| Safe Haskell | Safe |
|---|---|
| Language | Haskell2010 |
ReWire.Hyle.ToVerilog
Description
The Verilog backend on Hyle. With widths explicit and exact in the IR (doc/hyle.md, G1), expression emission is a per-construct template: no context-width reconstruction, no pattern compilation, no clock plumbing through the module tree (Hyle defns are always pure -- sequential externs are device-level instances), and the state machine is built from the device's explicit registers rather than reconstructed from the resumption layout.
Defns are emitted one module each (inlining decisions are made upstream by ReWire.Hyle.Transform.inline); the device becomes the top module: per-register current/next signals updated in a single clocked process, wire assignments for the device lets, and one instantiation per sequential-extern instance.
Documentation
compileProgram :: MonadError AstError m => Config -> Program -> m Device Source #
testbench :: Config -> Device -> [Ins] -> Module Source #
A testbench driving the device with interp-style inputs and printing outputs each cycle in the interpreter's YAML format (same protocol and timing as the VHDL testbench).
clockReset :: Config -> [Register] -> [Instance] -> (Maybe Text, Maybe Text) Source #
Clock and reset port names, when the device has them: no clock when there are no registers and no instances; no reset without a clock.
defnPortNames :: Defn -> [Text] Source #
Display names for a defn module's live (nonzero-width) parameters,
shared by the Verilog and VHDL backends: VHDL component declarations
must agree with the entity's port names (default binding matches
formals to entity ports by name), so both the entity and every call
site derive the same list from the defn alone. Each parameter name is
stripped of freshening tags and mangled; arg<i> is the fallback for
names that are SystemVerilog keywords, don't start with a letter or
underscore, or duplicate an earlier port (positionally, compared
case-folded: VHDL basic identifiers are case-insensitive). The result
port is always res, seeded into the dedupe so no parameter takes it.
lastComponent :: Text -> Text Source #
The text after the last . of a qualified name (e.g. main.getIns ->
getIns): the seed for instance labels.