Index - O
| occCounts | ReWire.Eidos.Subst |
| occIds | ReWire.Eidos.Subst |
| odd | |
| 1 (Function) | ReWire.Bits |
| 2 (Function) | ReWire.FiniteComp |
| One | ReWire.Verilog.Syntax |
| one | |
| 1 (Function) | ReWire.BitWord |
| 2 (Function) | ReWire.Bits |
| one' | ReWire.BitWord |
| ones | ReWire.BitVector |
| Op | ReWire.Hyle.Syntax |
| opName | ReWire.Hyle.Syntax |
| opResultSize | ReWire.Hyle.Syntax |
| optimize | ReWire.Hyle.Transform |
| optimizeProc | ReWire.Synolon.Transform |
| Or | |
| 1 (Data Constructor) | ReWire.Verilog.Syntax |
| 2 (Data Constructor) | ReWire.Hyle.Syntax |
| 3 (Data Constructor) | Embedder.Builtins, ReWire.Builtins |
| originArgs | ReWire.Eidos.Syntax, ReWire.Synolon.Syntax |
| originName | ReWire.Eidos.Syntax, ReWire.Synolon.Syntax |
| originTag | ReWire.Eidos.Naming |
| otherwise | ReWire.Prelude |
| Out | ReWire.VHDL.Syntax |
| outFile | ReWire.Config, Embedder.Config |
| OutFlag | ReWire.Config, Embedder.Config |
| outFlags | ReWire.Config, Embedder.Config |
| Output | ReWire.Verilog.Syntax |
| outputSigs | ReWire.Config, Embedder.Config |
| Outs | ReWire.Hyle.Interp |